MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-CIRCUITS DUE TO ELECTROSTATIC DISCHARGE

Abstract
MOS transistors have been used as sensors to study non-catastrophic effects of electrostatic discharges in input stages with protection circuits as well as output stages of VLSI circuits. Stress voltages far below the destructive level were found to cause both, severe threshold voltage shifts and transconductance degradation. As a result a reduction in circuit reliability is observed. To prevent degradation, selected and improved ESD protection circuits have to be used. It will be shown that the standard criterium for ESD-hardness needs to be extended in order to account for these requirements.