| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-283 - C4-286 | |
| DOI | https://doi.org/10.1051/jphyscol:1988458 | |
ESSDERC 88
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-283-C4-286
DOI: 10.1051/jphyscol:1988458
Siemens AG, Microelectronic Technology Center, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-283-C4-286
DOI: 10.1051/jphyscol:1988458
GATE OXIDE QUALITY OF DRAM TRENCH CAPACITORS
S. RÖHL, M. ENGELHARDT, W.-U. KELLNER et A. SCHLEMMSiemens AG, Microelectronic Technology Center, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
Abstract
The quality of thin trench capacitor oxide dielectric for 4M and 16M DRAM generations is investigated by leakage current and time dependent dielectric breakdown measurements. Geometric trench shape and surface smoothness influence leakage currents and thus dielectric lifetime, but etch chemistry, side wall redeposition and contamination are more important factors which reduce gate oxide quality. It is shown that silicon removing post treatments regain gate oxide quality comparable to planar capacitors.