Numéro
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 88
18th European Solid State Device Research Conference
Page(s) C4-537 - C4-540
DOI https://doi.org/10.1051/jphyscol:19884112
ESSDERC 88
18th European Solid State Device Research Conference

J. Phys. Colloques 49 (1988) C4-537-C4-540

DOI: 10.1051/jphyscol:19884112

A COMPARISON OF TRENCH FILLING MATERIALS FOR SUB-MICRON CMOS

P.H. BOLBOT, M.C. ROBERTS et P.L. MEDHURST

Plessey Research Caswell Ltd., Caswell, Towcester, Northants., GB-NN12 8EQ, Great-Britain


Abstract
This paper discusses the fabrication of trench isolated CMOS using different filling materials. Preliminary studies of dielectric films have been compared with polysilicon for trench-filling ease ; resistance of trench material to subsequent erosion, thermal stability, stress generation and parasitic transistor supression. Polysilicon filling is less sensitive to trench shape for ease of processing well-filled trenches. Corner effects seen with oxide-filled trenches (similar to those seen on SOI) can be eliminated using the polysilicon filling technique and processing modifications can be made to totally supress parasitic sidewall devices. The additional use of polysilicon as resistors or capacitors makes it the most favoured technique.