Numéro
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 88
18th European Solid State Device Research Conference
Page(s) C4-669 - C4-672
DOI https://doi.org/10.1051/jphyscol:19884140
ESSDERC 88
18th European Solid State Device Research Conference

J. Phys. Colloques 49 (1988) C4-669-C4-672

DOI: 10.1051/jphyscol:19884140

INTERFACE STATE GENERATION IN NMOS TRANSISTORS DURING HOT CARRIER STRESS AT LOW TEMPERATURES

D. KRISHNA RAO, M.M. HEYNS et R.F. DE KEERSMAECKER

Interuniversity Microelectronics Center (IMEC vzw), Kapeldreef, 75, B-3030 Leuven, Belgium


Abstract
The generation of interface states in NMOS transistors during hot carrier injection is investigated at temperatures between 300 and 75 K. It is found that hot carrier stress at low temperatures induces a higher number of interface states than at 300 K. The generation rate of interface states can be fitted with a power law as a function of stressing time with a value of the exponent which is independent of the stressing temperature. A similar dependence on the stressing gate voltage is found for hot carrier stress at 75 K and 300 K. The results suggest a temperature independent mechanism of interface state creation. The important role of oxide hole traps in the interface state generation at low temperatures is demonstrated using two-step experiments.