| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-97 - C4-100 | |
| DOI | https://doi.org/10.1051/jphyscol:1988420 | |
ESSDERC 88
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-97-C4-100
DOI: 10.1051/jphyscol:1988420
Siemens AG, Corporate Research, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-97-C4-100
DOI: 10.1051/jphyscol:1988420
WELL - OPTIMIZATION FOR HIGH SPEED BICMOS TECHNOLOGIES
H. KLOSE, T. MEISTER, B. HOFFMANN, J. WENG et B. PFÄFFELSiemens AG, Corporate Research, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
Abstract
A high speed BICMOS process with a polysilicon bipolar transistor is presented. Using this technology the well optimization is outlined. Different approaches to construct the well are compared to improve the high current behaviour of the bipolar transistor. Influences on the parasitics are discussed. Using the optimized process version bipolar transistors with a cut-off frequency of 9.5 GHz were fabricated.