| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-25 - C4-28 | |
| DOI | https://doi.org/10.1051/jphyscol:1988403 | |
ESSDERC 88
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-25-C4-28
DOI: 10.1051/jphyscol:1988403
IBM Research Division, Thomas J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, U.S.A.
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-25-C4-28
DOI: 10.1051/jphyscol:1988403
A HIGH PERFORMANCE LIQUID-NITROGEN CMOS SRAM TECHNOLOGY
J.Y.-C. SUN, S. KLEPNER, Y. TAUR, H. HANAFI, P. RESTLE, T. BUCELOT, K. PETRILLO, R. DENNARD, S. SCHUSTER, T. CHAPPELL, B. CHAPPELL et D. HEIDELIBM Research Division, Thomas J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, U.S.A.
Abstract
A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5µm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6µm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.