| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-571 - C4-574 | |
| DOI | https://doi.org/10.1051/jphyscol:19884120 | |
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-571-C4-574
DOI: 10.1051/jphyscol:19884120
USE OF A GATE DELAY EXPRESSION TO COMPARE SELF-ALIGNED SILICON BIPOLAR AND AlGaAs/GaAs HETEROJUNCTION BIPOLAR TECHNOLOGIES
P. ASHBURN1, A.A. REZAZADEH2, E.F. CHOR3 et A. BRUNNSCHWEILER11 Department of Electronics and Computer Science, University of Southampton, Southampton, Great-Britain
2 GEC Hirst Research Centre, East Lane, Wembley, Middlesex, Great-Britain
3 Department of Electrical Engineering, National university of Singapore, Kent Ridge, Singapore
Abstract
A comparison is made of the performance of silicon bipolar and AlGaAs/GaAs heterojunction bipolar technologies for high-speed ECL circuits . Gate delays are calculated for state of the art technologies using a quasi-analytical equation which expresses the gate delay in terms of all the time constants in the circuit . Transistor parameters are used as input to the gate delay expression and these are calculated using either device simulation programs or approximate analytical expressions. A one to one comparison i s made possible by the use of an idealised but realistic , transistor layout compatible wit bot technologies. For an emitter width of lum, a collector current of 2 x 104A/cm2, and a unity fan-out, gate delays of 26.9 and 12.3ps are predicted for silicon and AlGaAs/GaAs technologies respectively. On scaling to 0.4µm geometries, these delays decrease to 17.2 and 11.4ps. The gate delay expression is used to identify the dominant time constants of the circuit , and hence the most promising options for process and circuit optimisation.