Numéro
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 88
18th European Solid State Device Research Conference
Page(s) C4-471 - C4-480
DOI https://doi.org/10.1051/jphyscol:1988499
ESSDERC 88
18th European Solid State Device Research Conference

J. Phys. Colloques 49 (1988) C4-471-C4-480

DOI: 10.1051/jphyscol:1988499

FUTURE BIPOLAR DEVICE STRUCTURES

H. GOTO

Bipolar Process Engineering Department, Fujitsu Limited, 1015, Kamikodanaka, Nakahara, Kawasaki 211, Japan


Abstract
Recently developed bipolar device structures including their problems and future trends are reviewed. Polysilicon emitter-base self-aligned structures and trench isolation techniques are becoming key elements for high performance bipolar ECL device structures, by which parasitic capacitances and resistances have been reduced drastically. In order to get further improved performance, smaller parasitic capacitances associated with the pull-up resistor as well as high cutoff frequency are required. Wafer-direct-bonded SOI structures are the promising candidate, while the base resistance and the cutoff frequency should be optimized moderately. The most serious problem is the power dissipation of ECL-type circuits. Smaller logic swings and low temperature operation should be also considered.