| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-205 - C4-208 | |
| DOI | https://doi.org/10.1051/jphyscol:1988442 | |
ESSDERC 88
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-205-C4-208
DOI: 10.1051/jphyscol:1988442
1 Universität Duisburg, Halbleitertechnik/ Halbleitertechnologie, Sonderforschungsbereich 254, D-4100 Duisburg, F.R.G
2 Forschungsinstitut der Deutschen Bundespost, D-6100 Darmstadt, F.R.G.
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-205-C4-208
DOI: 10.1051/jphyscol:1988442
InGaAs SINGLE- AND DUAL-GATE HIGH-SPEED FETs : PREPARATION AND PERFORMANCE
K. STEINER1, K. NTIKBASANIS1, U. SEILER1, K. HEIME1 et E. KUPHAL21 Universität Duisburg, Halbleitertechnik/ Halbleitertechnologie, Sonderforschungsbereich 254, D-4100 Duisburg, F.R.G
2 Forschungsinstitut der Deutschen Bundespost, D-6100 Darmstadt, F.R.G.
Abstract
The preparation and performance of self-aligned single- and dual-gate InGaAs JFETs is discussed. Single-gate InGaAs JFETs exhibit maximum extrinsic transconductance of 350, 275 and 140 mS/mm at a gate length of 0.5, 1.5 and 3.5 µm, respectively. High overall potential barriers at the channel substrate heterointerface are necessary for control of threshold voltage uniformity over a wide range of gate lengths. For the first time device behaviour of self-aligned dual-gate InGaAs JFET is demonstrated.