| Numéro |
J. Phys. Colloques
Volume 49, Numéro C4, Septembre 1988
ESSDERC 8818th European Solid State Device Research Conference |
|
|---|---|---|
| Page(s) | C4-503 - C4-506 | |
| DOI | https://doi.org/10.1051/jphyscol:19884104 | |
ESSDERC 88
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-503-C4-506
DOI: 10.1051/jphyscol:19884104
Siemens AG, Microelectronic Technology Center, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
18th European Solid State Device Research Conference
J. Phys. Colloques 49 (1988) C4-503-C4-506
DOI: 10.1051/jphyscol:19884104
A SELF ALIGNED CONTACT PROCESS WITH IMPROVED SURFACE PLANARIZATION
K.H. KÜSTERS, W. SESSELMANN, H. MELZNER et B. FRIESELSiemens AG, Microelectronic Technology Center, Otto-Hahn-Ring 6, D-8000 München 83, F.R.G.
Abstract
A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hole is overlapping gate and field oxide. A thin nitride/thin poly-Si/oxide multilayer allows a contact hole etch, which does not significantly affect the oxide isolation of the gate and the field oxide. After acting as etch stop, the poly-Si is changed into oxide by selective oxidation. The new process offers an improved reflow of isolation oxide and contact hole rounding.